1. Field of the Invention
The present invention relates to a method of forming metallization and contact structures in an integrated circuit, using a xe2x80x9cdual damascenexe2x80x9d-like procedure.
2. Discussion of the Background
During the preparation of integrated circuits, electrical connections between active regions of a semiconductor device are necessary.
One method of preparation involves the use of self-aligned contact (SAC) technology, which may comprise forming an opening through a dielectric material to an active region of a semiconductor device, wherein a gate structure adjacent to the active region may be protected during the contact opening etching step by encapsulation with a material which may have a lower etching rate than that of the surrounding dielectric material. In this fashion, one may reduce the total area consumed by functional circuitry while minimizing damage to the gate structure that might otherwise result from small errors in aligning the contact hole with the underlying conductive region.
After such an opening has been formed, it may be filled with a conductive material and planarized to form a self-aligned contact. Two or more SACs may be electrically connected by a local trench which may be formed by patterning a metal layer, such that the metal layer electrically connects the SACs, followed by depositing and optionally planarizing a dielectric material.
A xe2x80x9cdamascenexe2x80x9d metallization layer is an alternative to the pattered metal layer described above. A xe2x80x9cdamascenexe2x80x9d metal layer is one where a trench or trough is formed in a dielectric material layer, then the trench is filled with a conductive metal. Damascene processes are becoming more widely used in semiconductor processing.
Problems observed in the interface between the SAC and the interconnect formed by damascene metallization have produced xe2x80x9cdual damascenexe2x80x9d processes, in which a channel is formed in a trench dielectric and an opening is formed in an underlying contact dielectric, both of which are then filled with a metal. This technology offers the advantages of simultaneously forming the contact and interconnect, which can result in reduced processing steps and a more highly conductive interface between the contact and interconnect structures.
Yen U.S. Pat. No. 5,861,676, reports a method of forming interconnects and contacts between elements in a semiconductor or integrated circuit.
Avanzino et al. U.S. Pat. No. 5,795,823 reports the fabrication of conductive lines and connecting vias using dual damascene with only one mask pattern. This is also reported by Avanzino et al. in U.S. Pat. No. 5,614,765.
Dai U.S. Pat. No. 5,877,076 reports a dual damascene process using opposite type two-layered photoresist.
Dai et al U.S. Pat. No. 5,876,075 reports forming dual damascene patterns using a single photoresist process.
Dai U.S. Pat. No. 5,882,996 discloses a method for patterning dual damascene interconnections using a developer soluble ARC interstitial layer.
Huang et al. U.S. Pat. No. 5,635,423 reports a modified dual damascene process in which an initial opening in a trench dielectric is enlarged while simultaneously extending a via opening through an etch stop layer and a via dielectric.
Qiao and Nulty, U.S. Ser. No. 326,432, filed on Jun. 4, 1999, report a method and structure for making self-aligned contacts.
Blosse et al. IEEE 1999 International Interconnect Technology Conference, p 215-217 reports a comparison between counterbore dual damascene and self-aligned dual damascene in forming aluminum interconnects using PVD.
In spite of known techniques for forming contacts and interconnects, increases in device density and demands for increased processing efficiency, have spurred new efforts to effectively produce semiconductor interconnections.
One embodiment of the present invention involves a method of preparing interconnects and self-aligned contact structures through a dual damascene process.
Another embodiment of the present invention involves a dual damascene method of forming metallization and self-aligned contact structures to active regions of a semiconductor device controlled by a gate structure.
Another embodiment of the present invention involves a dual damascene method of forming metallization and contact structures to an active region of a semiconductor device controlled by a gate structure, in which the gate is protected during etching of the contact hole.
Another embodiment of the present invention involves a dual damascene method of forming metallization and contact structures to an active region of a semiconductor device in which etching a contact dielectric layer is effectively prevented by an overlying etch stop layer.
Another embodiment of the present invention involves a dual damascene method of forming metallization and contact structures to an active region of a semiconductor device in which the gate may be protected during etching the contact hole and in which etching of the contact hole through the contact dielectric layer may be conducted in the absence of a patterned photoresist.
These and other embodiments of the present invention are made possible by a dual damascene method in which etching through the trench and contact dielectric layers are conducted using self-aligned contact techniques.